Test LB+PPO0536

Executions for behaviour: "0:R0=64 ; 1:R0=0"

ARM LB+PPO0536
"PodRW Rfe DpDatadW Rfe DpAddrdR PosRR"
Cycle=Rfe DpAddrdR PosRR PodRW Rfe DpDatadW
Relax=
Safe=Rfe PosRR Pod*W DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodRW Rfe DpDatadW Rfe DpAddrdR PosRR
{
%z0=z; %x0=x;
%x1=x; %y1=y; %z1=z;
}
 P0           | P1              ;
 LDR R0,[%z0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | EOR R1,R0,R0    ;
 ADD R1,R1,#1 | LDR R2,[R1,%y1] ;
 STR R1,[%x0] | LDR R3,[%y1]    ;
              | MOV R4,#1       ;
              | STR R4,[%z1]    ;
Observed
    0:R0=64; 1:R0=0;