Test LB+data+fri-rfi-fri-rfi-addr+OK

Executions for behaviour: "0:R0=0 ; 1:R0=0 ; 1:R2=1 ; 1:R4=1 ; y=1"

Executions for behaviour: "0:R0=0 ; 1:R0=0 ; 1:R2=3 ; 1:R4=1 ; y=1"

Executions for behaviour: "0:R0=0 ; 1:R0=0 ; 1:R2=1 ; 1:R4=3 ; y=1"

Executions for behaviour: "0:R0=1 ; 1:R0=0 ; 1:R2=1 ; 1:R4=3 ; y=1"

Executions for behaviour: "0:R0=0 ; 1:R0=0 ; 1:R2=3 ; 1:R4=3 ; y=1"

Executions for behaviour: "0:R0=1 ; 1:R0=0 ; 1:R2=3 ; 1:R4=3 ; y=1"

Executions for behaviour: "0:R0=0 ; 1:R0=0 ; 1:R2=3 ; 1:R4=3 ; y=3"

Executions for behaviour: "0:R0=1 ; 1:R0=0 ; 1:R2=3 ; 1:R4=3 ; y=3"

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R2=3 ; 1:R4=3 ; y=3"

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 1:R2=3 ; 1:R4=3 ; y=3"

ARM LB+data+fri-rfi-fri-rfi-addr+OK
"DpDatadW Rfe Fri Rfi Fri Rfi DpAddrdW Rfe"
(* Combining three LB+PPO tests *)
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe Fri Rfi Fri Rfi DpAddrdW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1              ;
 LDR R0,[%x0] | LDR R0,[%y1]    ;
 EOR R1,R0,R0 | MOV R1,#2       ;
 ADD R1,R1,#1 | STR R1,[%y1]    ;
 STR R1,[%y0] | LDR R2,[%y1]    ;
              | MOV R3,#3       ;
              | STR R3,[%y1]    ;
              | LDR R4,[%y1]    ;
              | EOR R5,R4,R4    ;
              | MOV R6,#1       ;
              | STR R6,[R5,%x1] ;
Observed
    0:R0=0; 1:R0=0; 1:R2=1; 1:R4=1; y=1;
and 0:R0=0; 1:R0=0; 1:R2=3; 1:R4=1; y=1;
and 0:R0=0; 1:R0=0; 1:R2=1; 1:R4=3; y=1;
and 0:R0=1; 1:R0=0; 1:R2=1; 1:R4=3; y=1;
and 0:R0=0; 1:R0=0; 1:R2=3; 1:R4=3; y=1;
and 0:R0=1; 1:R0=0; 1:R2=3; 1:R4=3; y=1;
and 0:R0=0; 1:R0=0; 1:R2=3; 1:R4=3; y=3;
and 0:R0=1; 1:R0=0; 1:R2=3; 1:R4=3; y=3;
and 0:R0=0; 1:R0=1; 1:R2=3; 1:R4=3; y=3;
and 0:R0=1; 1:R0=1; 1:R2=3; 1:R4=3; y=3;