Test LB+addrs+WW

ARM LB+addrs+WW
"DpAddrdW PodWW Rfe DpAddrdW PodWW Rfe"
Prefetch=
Orig=DpAddrdW PodWW Rfe DpAddrdW PodWW Rfe
{
%x0=x; %y0=y; %z0=z;
%z1=z; %a1=a; %x1=x;
}
 P0               | P1               ;
 LDR R0, [%x0]    | LDR R0, [%z1]    ;
 EOR R1,R0,R0     | EOR R1,R0,R0     ;
 MOV R2, #1       | MOV R2, #1       ;
 STR R2, [R1,%y0] | STR R2, [R1,%a1] ;
 MOV R3, #1       | MOV R3, #1       ;
 STR R3, [%z0]    | STR R3, [%x1]    ;
exists
(0:R0=1 /\ 1:R0=1)