Test LB0002

Executions for behaviour: "0:R0=1 ; 1:R0=1"

ARM LB0002
"DpDatadW Rfe PosRR DpAddrdR DpAddrdW Rfe"
Cycle=Rfe PosRR DpAddrdR DpAddrdW Rfe DpDatadW
Relax=[Rfe,DpDatadW,Rfe]
Safe=PosRR DpAddrdW DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe PosRR DpAddrdR DpAddrdW Rfe
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1              ;
 LDR R0,[%x0] | LDR R0,[%y1]    ;
 EOR R1,R0,R0 | LDR R1,[%y1]    ;
 ADD R1,R1,#1 | EOR R2,R1,R1    ;
 STR R1,[%y0] | LDR R3,[R2,%z1] ;
              | EOR R4,R3,R3    ;
              | MOV R5,#1       ;
              | STR R5,[R4,%x1] ;
Observed
    0:R0=1; 1:R0=1;