Test LB+PPO0146

Executions for behaviour: "0:R0=1 ; 1:R0=1"

ARM LB+PPO0146
"PodWW Rfe DpDatadW Rfe PosRR DpDatadW PosWR DpAddrdR DpDatadW"
Cycle=Rfe PosRR DpDatadW PosWR DpAddrdR DpDatadW PodWW Rfe DpDatadW
Relax=
Safe=Rfe PosWR PosRR Pod*W DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe PosRR DpDatadW PosWR DpAddrdR DpDatadW
{
%b0=b; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a; %b1=b;
}
 P0           | P1              ;
 LDR R0,[%b0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | LDR R1,[%x1]    ;
 ADD R1,R1,#1 | EOR R2,R1,R1    ;
 STR R1,[%x0] | ADD R2,R2,#1    ;
              | STR R2,[%y1]    ;
              | LDR R3,[%y1]    ;
              | EOR R4,R3,R3    ;
              | LDR R5,[R4,%z1] ;
              | EOR R6,R5,R5    ;
              | ADD R6,R6,#1    ;
              | STR R6,[%a1]    ;
              | MOV R7,#1       ;
              | STR R7,[%b1]    ;
Observed
    0:R0=1; 1:R0=1;