Test S+PPO116

Executions for behaviour: "1:R0=1 ; x=2"

ARM S+PPO116
"Wse DMBdWW Rfe PosRR DpCtrldW PosWR DpDatadW PosWR DpAddrdW"
Cycle=Rfe PosRR DpCtrldW PosWR DpDatadW PosWR DpAddrdW Wse DMBdWW
Relax=
Safe=Rfe Wse PosWR PosRR DMBdWW DpAddrdW DpDatadW DpCtrldW
Prefetch=0:x=F,1:x=W
Orig=Wse DMBdWW Rfe PosRR DpCtrldW PosWR DpDatadW PosWR DpAddrdW
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | CMP R1, R1       ;
 MOV R1, #1    | BNE LC00         ;
 STR R1, [%y0] | LC00:            ;
               | MOV R2, #1       ;
               | STR R2, [%z1]    ;
               | LDR R3, [%z1]    ;
               | EOR R4,R3,R3     ;
               | ADD R4, R4, #1   ;
               | STR R4, [%a1]    ;
               | LDR R5, [%a1]    ;
               | EOR R6,R5,R5     ;
               | MOV R7, #1       ;
               | STR R7, [R6,%x1] ;
Observed
    1:R0=1; x=2;