Test MP0124

Executions for behaviour: "1:R0=1 ; 1:R3=1 ; x=2"

ARM MP0124
"DMBdWW Rfe PosRR DpDatadW PosWR Fre"
Cycle=Rfe PosRR DpDatadW PosWR Fre DMBdWW
Relax=[Fre,DMBdWW,Rfe]
Safe=PosWR PosRR DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe PosRR DpDatadW PosWR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | LDR R0,[%y1] ;
 STR R0,[%x0] | LDR R1,[%y1] ;
 DMB          | EOR R2,R1,R1 ;
 MOV R1,#1    | ADD R2,R2,#1 ;
 STR R1,[%y0] | STR R2,[%x1] ;
              | LDR R3,[%x1] ;
Observed
    1:R0=1; 1:R3=1; x=2;