Test S0168

Executions for behaviour: "1:R0=1 ; x=2"

ARM S0168
"DMBdWW Rfe PosRR DpAddrdR PodRW Wse"
Cycle=Rfe PosRR DpAddrdR PodRW Wse DMBdWW
Relax=[Wse,DMBdWW,Rfe]
Safe=PosRR PodRW DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe PosRR DpAddrdR PodRW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1              ;
 MOV R0,#2    | LDR R0,[%y1]    ;
 STR R0,[%x0] | LDR R1,[%y1]    ;
 DMB          | EOR R2,R1,R1    ;
 MOV R1,#1    | LDR R3,[R2,%z1] ;
 STR R1,[%y0] | MOV R4,#1       ;
              | STR R4,[%x1]    ;
Observed
    1:R0=1; x=2;