Test MP+PPO849

Executions for behaviour: "1:R0=1 ; 1:R4=0"

ARM MP+PPO849
"Fre DMBdWW Rfe PosRR DpAddrdR PosRR"
Cycle=Rfe PosRR DpAddrdR PosRR Fre DMBdWW
Relax=
Safe=Rfe Fre PosRR DMBdWW DpAddrdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpAddrdR PosRR
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | EOR R2,R1,R1     ;
 MOV R1, #1    | LDR R3, [R2,%x1] ;
 STR R1, [%y0] | LDR R4, [%x1]    ;
Observed
    1:R0=1; 1:R4=0;