Test MP+PPO566

Executions for behaviour: "1:R0=1 ; 1:R4=1 ; x=2"

ARM MP+PPO566
"Fre DMBdWW Rfe PosRR DpAddrdW PosWR"
Cycle=Rfe PosRR DpAddrdW PosWR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRR DMBdWW DpAddrdW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpAddrdW PosWR
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | EOR R2,R1,R1     ;
 MOV R1, #1    | MOV R3, #1       ;
 STR R1, [%y0] | STR R3, [R2,%x1] ;
               | LDR R4, [%x1]    ;
Observed
    1:R0=1; 1:R4=1; x=2;