Test LB+PPO0074

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; x=2"

ARM LB+PPO0074
"PodWW Rfe DpDatadW Rfe PosRR PosRW PosWR DpAddrdR DpAddrdW"
Cycle=Rfe PosRR PosRW PosWR DpAddrdR DpAddrdW PodWW Rfe DpDatadW
Relax=
Safe=Rfe PosWR PosRW PosRR Pod*W DpAddrdW DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe PosRR PosRW PosWR DpAddrdR DpAddrdW
{
%a0=a; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a;
}
 P0           | P1              ;
 LDR R0,[%a0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | LDR R1,[%x1]    ;
 ADD R1,R1,#1 | MOV R2,#2       ;
 STR R1,[%x0] | STR R2,[%x1]    ;
              | LDR R3,[%x1]    ;
              | EOR R4,R3,R3    ;
              | LDR R5,[R4,%y1] ;
              | EOR R6,R5,R5    ;
              | MOV R7,#1       ;
              | STR R7,[R6,%z1] ;
              | MOV R8,#1       ;
              | STR R8,[%a1]    ;
Observed
    0:R0=1; 1:R0=1; x=2;