Test CO-SBI

Executions for behaviour: "0:R1=1 ; 0:R2=1 ; 1:R1=1 ; 1:R2=2"

Executions for behaviour: "0:R1=2 ; 0:R2=1 ; 1:R1=2 ; 1:R2=2"

ARM CO-SBI

{0:R3=x; 1:R3=x;}

 P0          | P1          ;
 MOV R0,#1   | MOV R0,#2   ;
 STR R0,[R3] | STR R0,[R3] ;
 LDR R1,[R3] | LDR R1,[R3] ;
 LDR R2,[R3] | LDR R2,[R3] ;
Observed
    0:R1=1; 0:R2=1; 1:R1=1; 1:R2=2;
and 0:R1=2; 0:R2=1; 1:R1=2; 1:R2=2;