Test WRR+2W+addr+dmb

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; x=1"

ARM WRR+2W+addr+dmb
"Rfe DpAddrdR Fre DMBdWW Wse"
Cycle=Rfe DpAddrdR Fre DMBdWW Wse
Prefetch=0:x=F,1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=Rfe DpAddrdR Fre DMBdWW Wse
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1              | P2           ;
 MOV R0,#2    | LDR R0,[%x1]    | MOV R0,#1    ;
 STR R0,[%x0] | EOR R1,R0,R0    | STR R0,[%y2] ;
              | LDR R2,[R1,%y1] | DMB          ;
              |                 | MOV R1,#1    ;
              |                 | STR R1,[%x2] ;
Observed
    1:R0=1; 1:R2=0; x=1;