Test S+PPO712

Executions for behaviour: "1:R0=1 ; x=2"

ARM S+PPO712
"Wse DMBdWW Rfe PosRR DpCtrldW PosWR DpCtrldW PosWR DpCtrldW"
Cycle=Rfe PosRR DpCtrldW PosWR DpCtrldW PosWR DpCtrldW Wse DMBdWW
Relax=
Safe=Rfe Wse PosWR PosRR DMBdWW DpCtrldW
Prefetch=0:x=F,1:x=W
Orig=Wse DMBdWW Rfe PosRR DpCtrldW PosWR DpCtrldW PosWR DpCtrldW
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1            ;
 MOV R0, #2    | LDR R0, [%y1] ;
 STR R0, [%x0] | LDR R1, [%y1] ;
 DMB           | CMP R1, R1    ;
 MOV R1, #1    | BNE LC00      ;
 STR R1, [%y0] | LC00:         ;
               | MOV R2, #1    ;
               | STR R2, [%z1] ;
               | LDR R3, [%z1] ;
               | CMP R3, R3    ;
               | BNE LC01      ;
               | LC01:         ;
               | MOV R4, #1    ;
               | STR R4, [%a1] ;
               | LDR R5, [%a1] ;
               | CMP R5, R5    ;
               | BNE LC02      ;
               | LC02:         ;
               | MOV R6, #1    ;
               | STR R6, [%x1] ;
Observed
    1:R0=1; x=2;