Test MP+PPO952

Executions for behaviour: "1:R0=1 ; 1:R5=1 ; x=2 ; y=2"

ARM MP+PPO952
"Fre DMBdWW Rfe PosRW PosWR DpCtrldW PosWR PosRR"
Cycle=Rfe PosRW PosWR DpCtrldW PosWR PosRR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRW PosRR DMBdWW DpCtrldW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRW PosWR DpCtrldW PosWR PosRR
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0            | P1            ;
 MOV R0, #2    | LDR R0, [%y1] ;
 STR R0, [%x0] | MOV R1, #2    ;
 DMB           | STR R1, [%y1] ;
 MOV R1, #1    | LDR R2, [%y1] ;
 STR R1, [%y0] | CMP R2, R2    ;
               | BNE LC00      ;
               | LC00:         ;
               | MOV R3, #1    ;
               | STR R3, [%x1] ;
               | LDR R4, [%x1] ;
               | LDR R5, [%x1] ;
Observed
    1:R0=1; 1:R5=1; x=2; y=2;