Test MP+PPO327

Executions for behaviour: "1:R0=1 ; 1:R6=0"

ARM MP+PPO327
"Fre DMBdWW Rfe PosRR DpDatadW PosWR DpDatadW PosWR DpCtrlIsbdR"
Cycle=Rfe PosRR DpDatadW PosWR DpDatadW PosWR DpCtrlIsbdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRR DMBdWW DpDatadW DpCtrlIsbdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpDatadW PosWR DpDatadW PosWR DpCtrlIsbdR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1             ;
 MOV R0, #1    | LDR R0, [%y1]  ;
 STR R0, [%x0] | LDR R1, [%y1]  ;
 DMB           | EOR R2,R1,R1   ;
 MOV R1, #1    | ADD R2, R2, #1 ;
 STR R1, [%y0] | STR R2, [%z1]  ;
               | LDR R3, [%z1]  ;
               | EOR R4,R3,R3   ;
               | ADD R4, R4, #1 ;
               | STR R4, [%a1]  ;
               | LDR R5, [%a1]  ;
               | CMP R5, R5     ;
               | BNE LC00       ;
               | LC00:          ;
               | ISB            ;
               | LDR R6, [%x1]  ;
Observed
    1:R0=1; 1:R6=0;