Test LB0062

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; x=2"

Executions for behaviour: "0:R0=2 ; 1:R0=1 ; x=2"

ARM LB0062
"DpDatadW Rfe PosRR DpAddrdW PosWW Rfe"
Cycle=Rfe PosRR DpAddrdW PosWW Rfe DpDatadW
Relax=[Rfe,DpDatadW,Rfe]
Safe=PosWW PosRR DpAddrdW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe PosRR DpAddrdW PosWW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1              ;
 LDR R0,[%x0] | LDR R0,[%y1]    ;
 EOR R1,R0,R0 | LDR R1,[%y1]    ;
 ADD R1,R1,#1 | EOR R2,R1,R1    ;
 STR R1,[%y0] | MOV R3,#1       ;
              | STR R3,[R2,%x1] ;
              | MOV R4,#2       ;
              | STR R4,[%x1]    ;
Observed
    0:R0=1; 1:R0=1; x=2;
and 0:R0=2; 1:R0=1; x=2;