Test LB0029

Executions for behaviour: "0:R0=1 ; 1:R0=1"

ARM LB0029
"DpDatadW Rfe PosRR DpDatadW Rfe"
Cycle=Rfe PosRR DpDatadW Rfe DpDatadW
Relax=[Rfe,DpDatadW,Rfe]
Safe=PosRR DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe PosRR DpDatadW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 LDR R0,[%x0] | LDR R0,[%y1] ;
 EOR R1,R0,R0 | LDR R1,[%y1] ;
 ADD R1,R1,#1 | EOR R2,R1,R1 ;
 STR R1,[%y0] | ADD R2,R2,#1 ;
              | STR R2,[%x1] ;
Observed
    0:R0=1; 1:R0=1;