Test LB+data+pos-fri-rfi-ctrl

Executions for behaviour: "0:R0=1 ; 1:R0=0 ; 1:R1=1 ; 1:R3=2 ; y=2"

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 1:R1=1 ; 1:R3=2 ; y=2"

ARM LB+data+pos-fri-rfi-ctrl
"DpDatadW Rfe PosRR Fri Rfi DpCtrldW Rfe"
Cycle=Rfi DpCtrldW Rfe DpDatadW Rfe PosRR Fri
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpDatadW Rfe PosRR Fri Rfi DpCtrldW Rfe
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 LDR R0,[%x0] | LDR R0,[%y1] ;
 EOR R1,R0,R0 | LDR R1,[%y1] ;
 ADD R1,R1,#1 | MOV R2,#2    ;
 STR R1,[%y0] | STR R2,[%y1] ;
              | LDR R3,[%y1] ;
              | CMP R3,R3    ;
              | BNE LC00     ;
              | LC00:        ;
              | MOV R4,#1    ;
              | STR R4,[%x1] ;
Observed
    0:R0=1; 1:R0=0; 1:R1=1; 1:R3=2; y=2;
and 0:R0=1; 1:R0=1; 1:R1=1; 1:R3=2; y=2;