Test LB+PPO0263

Executions for behaviour: "0:R0=1 ; 1:R0=1"

ARM LB+PPO0263
"PodWW Rfe DpDatadW Rfe PosRR DpCtrldW PosWR DpCtrldW"
Cycle=Rfe PosRR DpCtrldW PosWR DpCtrldW PodWW Rfe DpDatadW
Relax=
Safe=Rfe PosWR PosRR Pod*W DpDatadW DpCtrldW
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe PosRR DpCtrldW PosWR DpCtrldW
{
%a0=a; %x0=x;
%x1=x; %y1=y; %z1=z; %a1=a;
}
 P0           | P1           ;
 LDR R0,[%a0] | LDR R0,[%x1] ;
 EOR R1,R0,R0 | LDR R1,[%x1] ;
 ADD R1,R1,#1 | CMP R1,R1    ;
 STR R1,[%x0] | BNE LC00     ;
              | LC00:        ;
              | MOV R2,#1    ;
              | STR R2,[%y1] ;
              | LDR R3,[%y1] ;
              | CMP R3,R3    ;
              | BNE LC01     ;
              | LC01:        ;
              | MOV R4,#1    ;
              | STR R4,[%z1] ;
              | MOV R5,#1    ;
              | STR R5,[%a1] ;
Observed
    0:R0=1; 1:R0=1;