| Model | Tegra2 | APQ8060 | A5X | A6X | Exynos5250 | Tegra3 | Exynos4412 | Exynos5410 | APQ8064 |
LB+PPO0536 | Forbid | Ok, 1/3.9G | No, 0/6.3G | No, 0/5.4G | No, 0/10G | No, 0/8.3G | No, 0/7.2G | No, 0/14G | No, 0/6.2G | No, 0/4.5G |
| | | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen |
Executions for behaviour: "0:R0=64 ; 1:R0=0"
ARM LB+PPO0536
"PodRW Rfe DpDatadW Rfe DpAddrdR PosRR"
Cycle=Rfe DpAddrdR PosRR PodRW Rfe DpDatadW
Relax=
Safe=Rfe PosRR Pod*W DpAddrdR DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodRW Rfe DpDatadW Rfe DpAddrdR PosRR
{
%z0=z; %x0=x;
%x1=x; %y1=y; %z1=z;
}
P0 | P1 ;
LDR R0,[%z0] | LDR R0,[%x1] ;
EOR R1,R0,R0 | EOR R1,R0,R0 ;
ADD R1,R1,#1 | LDR R2,[R1,%y1] ;
STR R1,[%x0] | LDR R3,[%y1] ;
| MOV R4,#1 ;
| STR R4,[%z1] ;
exists (0:R0=64 /\ 1:R0=0)