Test S+PPO230

	Model	Tegra2	APQ8060	A5X	A6X	Exynos5250	Tegra3	Exynos4412	Exynos5410	APQ8064
S+PPO230	Forbid	No, 0/3.9G	No, 0/5.1G	No, 0/4.7G	Ok, 17/10G	No, 0/8.3G	No, 0/6.4G	No, 0/14G	No, 0/6.2G	No, 0/4.5G
		Allow unseen	Allow unseen	Allow unseen		Allow unseen	Allow unseen	Allow unseen	Allow unseen	Allow unseen

Executions for behaviour: "1:R0=1 ; x=1 ; y=1"

Executions for behaviour: "1:R0=2 ; x=1 ; y=1"

Executions for behaviour: "1:R0=2 ; x=1 ; y=2"

ARM S+PPO230
"Wse DMBdWW Rfe PosRR PosRW PosWR DpAddrdR PosRR DpAddrdW"
Cycle=Rfe PosRR PosRW PosWR DpAddrdR PosRR DpAddrdW Wse DMBdWW
Relax=
Safe=Rfe Wse PosWR PosRW PosRR DMBdWW DpAddrdW DpAddrdR
Prefetch=0:x=F,1:x=W
Orig=Wse DMBdWW Rfe PosRR PosRW PosWR DpAddrdR PosRR DpAddrdW
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1               ;
 MOV R0, #2    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | MOV R2, #2       ;
 MOV R1, #1    | STR R2, [%y1]    ;
 STR R1, [%y0] | LDR R3, [%y1]    ;
               | EOR R4,R3,R3     ;
               | LDR R5, [R4,%z1] ;
               | LDR R6, [%z1]    ;
               | EOR R7,R6,R6     ;
               | MOV R8, #1       ;
               | STR R8, [R7,%x1] ;
Observed
    1:R0=1; x=1; y=1;
and 1:R0=2; x=1; y=1;
and 1:R0=2; x=1; y=2;