Model | Tegra2 | APQ8060 | A5X | A6X | Exynos5250 | Tegra3 | Exynos4412 | Exynos5410 | APQ8064 | |
MP+dmb+fri-rfi-ctrlisb | Forbid | No, 0/44G | Ok, 153k/10G | No, 0/9.0G | No, 0/14G | No, 0/8.3G | No, 0/62G | No, 0/34G | No, 0/6.3G | No, 0/4.7G |
Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen |
Executions for behaviour:
"1:R0=1 ; 1:R2=2 ; 1:R3=0 ; y=2"
ARM MP+dmb+fri-rfi-ctrlisb "DMBdWW Rfe Fri Rfi DpCtrlIsbdR Fre" Prefetch=1:x=T Com=Rf Fr Orig=DMBdWW Rfe Fri Rfi DpCtrlIsbdR Fre { %x0=x; %y0=y; %y1=y; %x1=x; } P0 | P1 ; MOV R0,#1 | LDR R0,[%y1] ; STR R0,[%x0] | MOV R1,#2 ; DMB | STR R1,[%y1] ; MOV R1,#1 | LDR R2,[%y1] ; STR R1,[%y0] | CMP R2,R2 ; | BNE LC00 ; | LC00: ; | ISB ; | LDR R3,[%x1] ; Observed 1:R0=1; 1:R2=2; 1:R3=0; y=2;