Model | Tegra3 | Exynos4412 | Exynos5410 | APQ8064 | |
DETOUR0687 | Forbid | Ok, 42/5.2G | No, 0/11G | No, 0/3.1G | No, 0/2.3G |
Allow unseen | Allow unseen | Allow unseen |
Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 1:R2=0"
ARM DETOUR0687 "DMBdWW Rfe DetourR DpCtrlIsbdR Fre" Cycle=Rfe DetourR DpCtrlIsbdR Fre DMBdWW Prefetch=0:x=F,0:y=W,1:y=F,1:x=T Com=Rf Fr Orig=DMBdWW Rfe DetourR DpCtrlIsbdR Fre { %x0=x; %y0=y; %y1=y; %x1=x; %y2=y; } P0 | P1 | P2 ; MOV R0,#1 | LDR R0,[%y1] | MOV R0,#2 ; STR R0,[%x0] | LDR R1,[%y1] | STR R0,[%y2] ; DMB | CMP R1,R1 | ; MOV R1,#1 | BNE LC00 | ; STR R1,[%y0] | LC00: | ; | ISB | ; | LDR R2,[%x1] | ; Observed 1:R0=1; 1:R1=1; 1:R2=0;