Test MP+dsb.st+ctrlisb

	Model	Tegra2	APQ8060	A5X	A6X	Exynos5250	Tegra3	Exynos4412	Exynos5410	APQ8064
MP+dsb.st+ctrlisb	Forbid	0/4.2G	0/7.6G	0/9.1G	0/13G	0/8.3G	0/7.0G	0/22G	0/6.3G	0/4.5G

Executions for behaviour: "1:R0=1 ; 1:R1=0"

ARM MP+dsb.st+ctrlisb
"DSB.STdWW Rfe DpCtrlIsbdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DSB.STdWW Rfe DpCtrlIsbdR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#1    | LDR R0,[%y1] ;
 STR R0,[%x0] | CMP R0,R0    ;
 DSB ST       | BNE LC00     ;
 MOV R1,#1    | LC00:        ;
 STR R1,[%y0] | ISB          ;
              | LDR R1,[%x1] ;
exists
(1:R0=1 /\ 1:R1=0)