Test MP+dmb.st+addr

	Model	Tegra2	APQ8060	A5X	A6X	Exynos5250	Tegra3	Exynos4412	Exynos5410	APQ8064
MP+dmb.st+addr	Forbid	0/4.2G	0/7.6G	0/9.1G	0/13G	0/8.3G	0/7.0G	0/22G	0/6.3G	0/4.5G

Executions for behaviour: "1:R0=1 ; 1:R2=0"

ARM MP+dmb.st+addr
"DMB.STdWW Rfe DpAddrdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.STdWW Rfe DpAddrdR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1              ;
 MOV R0,#1    | LDR R0,[%y1]    ;
 STR R0,[%x0] | EOR R1,R0,R0    ;
 DMB ST       | LDR R2,[R1,%x1] ;
 MOV R1,#1    |                 ;
 STR R1,[%y0] |                 ;
exists
(1:R0=1 /\ 1:R2=0)