Test REG01

PPC REG01
"Rfe LwSyncdRW Rfe SyncdRR Fre SyncdWR Fre"
Prefetch=0:x=T,1:x=F,1:y=W,2:y=F,2:z=T,3:z=F,3:x=T
Com=Rf Rf Fr Fr
Orig=Rfe LwSyncdRW Rfe SyncdRR Fre SyncdWR Fre
{
0:r2=x;
1:r2=x; 1:r4=y;
2:r2=y; 2:r4=z;
3:r2=z; 3:r4=x;
}
 P0           | P1           | P2           | P3           ;
 li r1,1      | lwz r1,0(r2) | lwz r1,0(r2) | li r1,1      ;
 stw r1,0(r2) | lwsync       | sync         | stw r1,0(r2) ;
              | li r3,1      | lwz r3,0(r4) | sync         ;
              | stw r3,0(r4) |              | lwz r3,0(r4) ;
exists
(1:r1=1 /\ 2:r1=1 /\ 2:r3=0 /\ 3:r3=0)