Test LB+dmb.sypl+po

AArch64 LB+dmb.sypl+po
"DMB.SYdRWPL RfeLP PodRW Rfe"
Cycle=Rfe DMB.SYdRWPL RfeLP PodRW
Relax=
Safe=Rfe PodRW DMB.SYdRW RfeLP
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DMB.SYdRWPL RfeLP PodRW Rfe
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=x;
}
 P0           | P1          ;
 LDR W0,[X1]  | LDR W0,[X1] ;
 DMB SY       | MOV W2,#1   ;
 MOV W2,#1    | STR W2,[X3] ;
 STLR W2,[X3] |             ;
Observed
    1:X0=1; 0:X0=1;